US 2008/0258790 A1 · Systems and Devices for Sub-threshold Data Capture

Abstract

Various systems and methods for capturing data are disclosed. For example, some embodiments of the present invention provide differential jam latches. Such differential jam latches include a data input, a latch input, and an output. Further, such differential jam latches include a PMOS stage and an NMOS stage. The PMOS stage includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor. The gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically coupled to an inverted version of the latch input. The gate of the third PMOS transistor is electrically coupled to the data input, and the gate of the fourth PMOS transistor is electrically coupled to an inverted version of the data input. The NMOS stage includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor. The gate of the first NMOS transistor and the gate of the second NMOS transistor are electrically coupled to the latch input. The gate of the third NMOS transistor is electrically coupled to the data input, and the gate of the fourth NMOS transistor is electrically coupled to an inverted version of the data input. In addition, the jam latches include two inverters. The PMOS stage is electrically coupled to a first node and a second node, and the NMOS stage is electrically coupled to the first node and the second node. The first inverter drives an inverted version of the signal on the first node to the second node, and the second inverter drives an inverted version of the signal on the second node to the first node.

Claims20

Dependent claims

A D type flip-flop circuit, the circuit comprising:

a data input;
a clock input;
a first differential jam latch, wherein the first differential jam latch has first output, and wherein the data input and the clock input are electrically coupled to the first differential jam latch;
a second differential jam latch, wherein the second differential jam latch has a second output, wherein the clock input is electrically coupled to the second differential jam latch, and wherein the first output is electrically coupled to the second differential jam latch as an input;
wherein upon assertion of the clock input at one assertion level, the first differential jam latch is transparent and the second differential jam latch is latched;
and
wherein upon assertion of the clock input at another assertion level, the first differential jam latch is latched and the second differential jam latch is transparent.

4 more elements

A sub-threshold storage device, the storage device comprising:

a differential jam latch, wherein the differential jam latch includes a data input, a latch input, and an output;
and wherein the differential jam latch includes:
a PMOS stage, wherein the PMOS stage includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor;
wherein the gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically coupled to an inverted version of the latch input;
wherein the gate of the third PMOS transistor is electrically coupled to the data input, and wherein the gate of the fourth PMOS transistor is electrically coupled to an inverted version of the data input;
and
an NMOS stage, wherein the NMOS stage includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor;
wherein the gate of the first NMOS transistor and the gate of the second NMOS transistor are electrically coupled to the latch input;
wherein the gate of the third NMOS transistor is electrically coupled to the data input, and wherein the gate of the fourth NMOS transistor is electrically coupled to an inverted version of the data input;
a first inverter;
a second inverter;
wherein the PMOS stage is electrically coupled to a first node and a second node, wherein the NMOS stage is electrically coupled to the first node and the second node, wherein the first inverter drives an inverted version of the signal on the first node to the second node, and wherein the second inverter drives an inverted version of the signal on the second node to the first node.

9 more elements

A scan flip-flop circuit, wherein the circuit comprises:

a data input;
a scan input;
a clock input;
a scan latch, wherein the scan latch has first output;
and wherein the data input, the scan input, and the clock input are electrically coupled to the scan latch as inputs;
a differential jam latch, wherein the differential jam latch has a second output, wherein the clock input is electrically coupled to the second differential jam latch as an input, and wherein the first output is electrically coupled to the second differential jam latch as an input;
wherein upon assertion of the clock input at a first assertion level, the scan latch is transparent and the differential jam latch is latched;
and
wherein upon assertion of the clock input at a second assertion level, the scan jam latch is latched and the differential jam latch is transparent.

6 more elements

Dependencies are inferred from the claim text.

Systems and Devices for Sub-threshold Data Capture

Life of this patent

Systems and Devices for Sub-threshold Data Capture

Life of this patent

Abstract

Claims20