Multi-Bit Programmable Frequency Divider
AssigneeNXP B.V.
InventorsWenyi Song, Geertjan Joordens
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Abstract
A multi-bit, programmable, modular digital frequency divider divides an input frequency by an m-bit integer divisor to produce an output frequency. The integer divisor re-initializes m-number of flip-flop stages with the divisor input at the end of every output clock. Each divisor bit is gated to a D-input through a respective data multiplexer controlled by a clock output. A run/initialize mode controller receives the input frequency and produces the divided output frequency and controls the timing of the re-initialization.
Claims6
A multi-bit, programmable, modular digital frequency divider for dividing an input frequency by an m-bit integer divisor to produce divided output frequency, wherein m-number of flip-flop stages are re-initialized with a divisor input at the completion of every output clock, and wherein each divisor bit is gated to a memory element through a respective data multiplexer controlled by a clock output, and wherein, a run/initialize mode controller is provided to receive said input frequency and produce a divided output frequency and to control timing of said re-initialization.
A multi-bit, programmable frequency divider, comprising:
- a run/initialize mode controller having a divider clock input “cki” and for producing a divider clock output “cko”;
- a plurality of m-number of flip-flop stages configured in a ring and each having a clock input, a D-input, and a Q-output;
- a corresponding plurality of m-number of data selectors connected to alternatively gate either a Q-output or divisor bit input to a D-input of a respective flip-flop stage according to said divider clock output “cko”;
- a corresponding plurality of m-number of clock selectors connected to alternatively gate either said divider clock input “cki” or previous stage's Q-output to a clock-input of a respective flip-flop stage according to said divider clock output “cko”.
Dependencies are inferred from the claim text.