Contact Scheme for MOSFETs

A semiconductor structure comprising:

• a substrate;
• a first Fin field-effect transistor (FinFET) at a top surface of the substrate, the first FinFET comprising:
• a first fin;
• a first gate dielectric on a top surface and sidewalls of the first fin;
• a first gate electrode on the first gate dielectric;
• a first source/drain region in a portion of the first fin uncovered by the first gate dielectric;
• and
• a first source/drain silicide region on the first source/drain region;
• a second FinFET at the top surface of the substrate, the second FinFET comprising:
• a second fin;
• a second gate dielectric on a top surface and sidewalls of the second fin;
• a second gate electrode on the second gate dielectric;
• a second source/drain region in a portion of the second fin uncovered by the second gate dielectric;
• and
• a second source/drain silicide region on the second source/drain region;
• a first inter-layer dielectric (ILD) over the first and the second FinFETs;
• a second ILD over the first ILD;
• and
• a contact electrically connected to the first and the second source/drain silicide regions, wherein the contact has a top surface substantially level with a top surface of the first ILD.

A semiconductor structure comprising:

• a semiconductor substrate;
• a field-effect transistor (FET) at a top surface of the semiconductor substrate, wherein the FET comprises:
• a gate electrode having a top surface higher than a top surface of the semiconductor substrate;
• and
• a source/drain region adjacent the gate electrode;
• a bottom metallization layer over the FET;
• a contact electrically connected to at least one of the gate electrode and the source/drain region, wherein the contact has a bottom surface lower than the top surface of the gate electrode, and a top surface lower than a bottom surface of the bottom metallization layer;
• and
• a dual damascene structure comprising a metal line in the bottom metallization layer, and a via between, and electrically connecting, the metal line and the contact.

A method for forming a semiconductor structure, the method comprising:

• providing a semiconductor substrate;
• forming a first inter-layer dielectric (ILD) over the semiconductor substrate;
• forming a contact extending from a top surface of the first ILD into the first ILD;
• forming a second ILD over the first ILD;
• forming an inter-metal dielectric (IMD) over the second ILD;
• and
• forming a dual damascene structure comprising a metal line in the IMD and a via in the second ILD, wherein the via contacts the contact.

A method for forming a semiconductor structure, the method comprising:

• providing a substrate;
• forming a first Fin field-effect transistor (FinFET) at a top surface of the substrate, the first FinFET comprising:
• a first fin;
• a first gate dielectric on a top surface and sidewalls of the first fin;
• a first gate electrode on the first gate dielectric;
• a first source/drain region in a portion of the first fin uncovered by the first gate dielectric;
• and
• a first source/drain silicide region on the first source/drain region;
• forming a second FinFET at a top surface of the substrate, the second FinFET comprising:
• a second fin;
• a second gate dielectric on a top surface and sidewalls of the second fin;
• a second gate electrode on the second gate dielectric;
• a second source/drain region in a portion of the second fin uncovered by the second gate dielectric;
• and
• a first source/drain silicide region on the first source/drain region;
• forming a first inter-layer dielectric (ILD) over the substrate;
• forming a contact electrically connected to the first and the second source/drain silicide regions, wherein the contact has a top surface substantially level a top surface of the first ILD;
• and
• forming a second ILD over the first ILD.