Substrate solution for back gate controlled sram with coexisting logic devices

A semiconductor structure comprising:

• at least one double gated logic device within at least one logic device region, wherein said at least one double gated logic device includes, from bottom to top, a back gate, a back gate dielectric, a body region, a front gate dielectric and a front gate, said body region of said logic device includes a doped channel;
• at least one double gated SWAM device within least one SWAM device region, wherein said at least one double gated SRAM device includes, from bottom to top, a back gate, a back gate dielectric, a body region, a front gate dielectric and a front gate, said body region of said SRAM device includes a non-doped channel and said back gate of said SWAM device has a higher doping level that said back gate of said logic device;
• and
• at least a buried insulating layer located beneath each of said back gates.

A semiconductor structure comprising:

• at least one double gated logic device within at least one logic device region, wherein said at least one double gated logic device includes, from bottom to top, a back gate, a back gate dielectric, a body region, a front gate dielectric and a front gate, said body region of said logic device includes a doped channel;
• at least one double gated SRAM device within least one SRAM device region, wherein said at least one double gated SRAM device includes, from bottom to top, a back gate, a back gate dielectric, a body region, a front gate dielectric and a front gate, said body region of said SWAM device includes a non-doped channel and said back gate of said SWAM device has a higher doping level that said back gate of said logic device;
• and
• a semiconductor substrate located beneath each of said back gates.