Semiconductor device and manufaturing method thereof

A semiconductor device comprising:

• a semiconductor pillar extending to a direction substantially perpendicular to a main surface of a semiconductor substrate;
• a gate insulating film covering a surface of the semiconductor pillar;
• an upper diffusion layer formed in an upper part of the semiconductor pillar;
• a lower diffusion layer formed in the lower external periphery part of the semiconductor pillar;
• a gate electrode encircling at least a channel region located between the upper diffusion layer and the lower diffusion layer;
• and
• a discharge layer formed at a lower center part of the semiconductor pillar, the discharge layer connecting the channel region to the semiconductor substrate.

A method of manufacturing a semiconductor device comprising:

• a first step of forming a trench and a projection in a semiconductor substrate by etching the semiconductor substrate;
• a second step of forming a lower electrode on the bottom of the trench;
• a third step of covering the lower electrode with an insulating film;
• a fourth step of forming a semiconductor pillar in the semiconductor substrate by etching a part of the projection;
• a fifth step of forming a gate insulating film to cover a surface of the semiconductor pillar;
• and
• a sixth step of forming an upper diffusion layer and a lower diffusion layer in an upper part and a lower part of the semiconductor pillar, respectively, so that the lower diffusion layer contacts with the lower electrode.

A method of manufacturing a semiconductor device, comprising:

• a first step of forming a semiconductor pillar on a semiconductor substrate;
• a second step of forming a gate insulating film covering a surface of the semiconductor pillar;
• a third step of forming an upper diffusion layer and a lower diffusion layer in an upper part and a lower part of the semiconductor pillar, respectively;
• and
• a fourth step of forming a discharge layer that connects a channel region located between the upper diffusion layer and the lower diffusion layer to the semiconductor substrate.