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US 2008/0258203 A1Published application
Stacked sonos memory
AssigneeQimonda AG
InventorsThomas Happ, Jan Boris Philipp
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes a first SONOS memory cell and a second SONOS memory cell. The second memory cell is stacked on the first memory cell.
Claims28
An integrated circuit comprising:
- a first SONOS memory cell;
- and
- a second SONOS memory cell, the second memory cell stacked on the first memory cell.
A memory comprising:
- a first memory cell comprising a first source, a first drain, a first tunnel dielectric material layer, a first trapping material layer, a first blocking dielectric material layer, and two first gates;
- and
- a second memory cell comprising a second source, a second drain, a second tunnel dielectric material layer, a second trapping material layer, a second blocking dielectric material layer, and two second gates, the second memory cell stacked on the first memory cell.
A method for fabricating a memory, the method comprising:
- providing a double silicon on insulator wafer including a first silicon layer and a second silicon layer;
- defining first lines of source/drain regions in the first silicon layer and second lines of source/drain regions in the second silicon layer above the first lines;
- etching lines into the wafer perpendicular to the first and second lines of source/drain regions to provide first bit lines in the first silicon layer and second bit lines in the second silicon layer;
- depositing a tunnel dielectric material layer, a trapping material layer, and a blocking dielectric material layer over exposed portions of the first bit lines and the second bit lines;
- etching the tunnel dielectric material layer, the trapping material layer, and the blocking dielectric material layer to provide a first chain of memory cells along each first bit line and a second chain of memory cells along each second bit line;
- and
- forming word lines over the etched blocking dielectric material layer to provide gates for each memory cell in each first chain and each second chain.
4 more elements
A method for fabricating a memory, the method comprising:
- providing a silicon on insulator wafer including a first silicon layer;
- defining first lines of source/drain regions in the first silicon layer and second lines of source/drain regions in the first silicon layer above the first lines;
- etching lines into the wafer perpendicular to the first and second lines of source/drain regions to provide lines of first silicon material;
- oxidizing a portion of each line of first silicon material to provide first bit lines and second bit lines above the first bit lines, the second bit lines isolated from the first bit lines by the oxidized portions;
- depositing a tunnel dielectric material layer, a trapping material layer, and a blocking dielectric material layer over exposed portions of the first bit lines and the second bit lines;
- etching the tunnel dielectric material layer, the trapping material layer, and the blocking dielectric material layer to provide a first chain of memory cells along each first bit line and a second chain of memory cells along each second bit line;
- and
- forming word lines over the etched blocking dielectric material layer to provide gates for each memory cell in each first chain and each second chain.
5 more elements
A method for fabricating a memory device, the method comprising:
- providing a bulk silicon wafer;
- defining first lines of source/drain regions in the bulk silicon and second lines of source/drain regions in the bulk silicon above the first lines of source/drain regions;
- etching lines into the wafer perpendicular to the first and second lines of source/drain regions to provide lines of silicon material;
- oxidizing a first portion and a second portion of each line of silicon material to provide first bit lines and second bit lines above the first bit lines, the second bit lines isolated from the first bit lines by the second oxidized portions, the first bit lines isolated from the bulk silicon by the first oxidized portions;
- depositing a tunnel dielectric material layer, a trapping material layer, and a blocking dielectric material layer over exposed portions of the first bit lines and the second bit lines;
- etching the tunnel dielectric material layer, the trapping material layer, and the blocking dielectric material layer to provide a first chain of memory cells along each first bit line and a second chain of memory cells along each second bit line;
- and
- forming word lines over the etched blocking dielectric material layer to provide gates for each memory cell in each first chain and each second chain.
5 more elements
An integrated circuit having a memory, the memory comprising:
- a first chain of finFET SONOS memory cells;
- a second chain of finFET SONOS memory cells, the second chain stacked on the first chain;
- a plurality of word lines, each word line coupled to a gate of one memory cell in the first chain and a gate of one memory cell in the second chain;
- a first select transistor configured to select the first chain to access a memory cell of the first chain;
- and
- a second select transistor configured to select the second chain to access a memory cell of the second chain.
3 more elements
A system comprising:
- a host;
- and
- a memory array communicatively coupled to the host, the memory array comprising:
- a first SONOS memory cell;
- and
- a second SONOS memory cell, the second memory cell stacked on the first memory cell.
3 more elements
Dependencies are inferred from the claim text.