Source and Drain Formation in Silicon on Insulator Device

A method of manufacturing a silicon on insulator semiconductor device, comprising:

• providing a substrate with a silicon layer above a support layer;
• forming a gate dielectric over the silicon layer, forming a gate over the gate dielectric and patterning the gate dielectric and gate;
• depositing an insulating spacer layer over the top of the gate, the sidewalls of the gate and gate dielectric and the silicon layer adjacent to the gate;
• carrying out a spacer etching step to etch the insulating spacer layer to form sidewall spacers on the sidewalls of the gate;
• depositing a Ni layer over the silicon layer, over the gate and over the spacers;
• forming doped amorphous silicon over the Ni layer over the and extending over the Ni layer on the gate;
• annealing the device at a temperature of 450° C. to 550° C. to recrystallise the amorphous silicon from the Ni layer adjacent to the silicon layer as doped crystalline silicon and regrowing the amorphous silicon over the gate and spacers as polysilicon;
• and
• selectively etching the polysilicon to remove the polysilicon from the spacers and gate leaving the doped crystalline silicon as source and drain.