Turbo decoder
AssigneeMarvell Israel (M.I.S.L) Ltd.
InventorUdi Shtalrid
Life of this patent
Estimating the term…
Abstract
A turbo decoder has at least two Bahl, Cocke, Jelinek, and Raviv (BCJR) processors in parallel, each in serial communication with respective interleavers. The BCJR processors and interleavers are in communication with a memory module that is internally split into non-overlapping memory banks. The turbo decoder includes respective sorter circuits in communication with the output of each BCJR processor/interleaver. A sorter circuit receives a data block from a BCJR processor/interleaver and directs the data block to the memory bank designated by an address assigned to the data block by an interleaver.
Claims25
A method comprising:
- receiving a first data block from a first decoder, the first data block having an assigned first memory address that is within a memory bank among a plurality of non-overlapping memory banks;
- receiving a second data block from a second decoder, the second data block having an assigned second memory address that is within the memory bank;
- communicating the first data block to a first buffer within a plurality of buffers;
- communicating the second data block to a second buffer within the plurality of buffers;
- selecting, according to a priority, either the first data block or the second data block from the plurality of buffers;
- and
- communicating the selected data block to the memory bank.
A wireless receiver comprising:
- a plurality of decoder circuits, including a first decoder circuit and a second decoder circuit, operative to decode encoded data blocks that are received by the wireless receiver;
- a plurality of non-overlapping memory banks, wherein each memory bank of the plurality of memory banks is in communication with each decoder circuit of the plurality of decoder circuits;
- and
- a routing circuit configured to communicate data that is decoded by the first decoder circuit to either one of a first memory bank and a second memory bank among the plurality of non-overlapping memory banks, and to selectively communicate data, decoded by the second decoder circuit, to either the first memory bank or the second memory bank.
A method comprising:
- assigning to a first data block of encoded data an address within a memory bank that is within a plurality of non-overlapping memory banks, wherein the plurality of memory banks are internal to a single memory module;
- sorting the first data block to a queue in communication with the memory bank;
- and
- reading the first data block from the queue and writing the first data block to the memory bank.
An apparatus comprising:
- an interleaver to assign to a first data block of encoded data an address within a memory bank within a plurality of memory banks, wherein the plurality of memory banks are internal to a single memory module;
- a sorter to sort the first data block to a queue in communication with the memory bank;
- and
- a router to read the first data block from the queue and communicate the first data block to the memory bank.
Dependencies are inferred from the claim text.