Reconfigurable array to compute digital algorithms

A reconfigurable array to compute digital algorithms to operate on digital data comprising:

• an integrated circuit comprising:
• a plurality of programmable clusters, each of said clusters comprising:
• a plurality of data inputs;
• a plurality of data outputs;
• a plurality of programming inputs;
• a plurality of logic units arranged as a matrix array;
• said matrix array of logic units coupled to said data inputs and said data outputs;
• at least some of said logic units comprising a Boolean logic computational unit having input terminals, output terminals, and programming terminals, said programming terminals receiving a corresponding portion of said programming inputs, said computational unit being controlled by said portion of programming inputs such that digital signals at said output terminals have a predetermined Boolean combinatorial relationship to said digital signals, said logic units being operated on a clocked basis such that each said logic unit is controlled by said programming inputs;
• each of said logic units comprising a selector coupled to said input terminals and programmable to selectively couple input data from either said data inputs or output terminals of one or more other computational units to said computational unit;
• and
• an array of programmable interconnects interconnecting said data inputs of said matrix array and said output terminals of each of said logic units with input terminals of others of said logic units and to said data outputs of said matrix array;
• each of said logic units and each of said selectors and said array of programmable interconnects being operated on a clocked basis such Boolean functionality is determined during each clock cycle.

A method for computing digital algorithms to operate on digital data comprising:

• providing an integrated circuit comprising having a plurality of data inputs, a plurality of data outputs and a plurality of programming inputs;
• providing on said integrated circuit a plurality of logic units;
• arranging said plurality of logic units as a matrix array;
• coupling said matrix array of logic units to said data inputs and said data outputs;
• providing at least some of said logic units as a Boolean logic computational unit each having input terminals, output terminals, and programming terminals;
• receiving at said programming terminals of each of said logic units a corresponding portion of said programming inputs;
• controlling each said logic unit by said corresponding portion of programming inputs such that digital signals at said output terminals have a predetermined Boolean combinatorial relationship to said digital signals;
• operating each of said logic units on a clocked basis such that each said logic unit is controlled by said corresponding portion of said programming inputs;
• providing each of said logic units with a selector coupled to said input terminals and programmable to selectively couple input data from either said data inputs or output terminals of one or more other computational units to said computational unit;
• providing an array of programmable interconnects interconnecting said data inputs of said matrix array and said output terminals of each of said logic units with input terminals of others of said logic units;
• and
• operating each of said logic units and each of said selectors and said array of programmable interconnects on a clocked basis such Boolean functionality is determined during each clock cycle.

A method for computing digital algorithms to operate on digital data, comprising:

• providing an integrated circuit comprising having a plurality of data inputs, a plurality of data outputs and a plurality of programming inputs;
• providing on said integrated circuit a plurality of clusters of logic units, each of said clusters comprising a plurality of logic units arranged as a matrix array;
• providing at least some of said logic units as a Boolean logic computational unit each having input terminals, output terminals, and programming terminals;
• receiving at said programming terminals of each of said logic units a corresponding portion of said programming inputs;
• controlling each said logic unit by said corresponding portion of programming inputs such that digital signals at said output terminals have a predetermined Boolean combinatorial relationship to digital signals at said input terminals;
• operating each of said logic units on a clocked basis such that each said logic unit is controlled by said corresponding portion of said programming inputs;
• providing each of said logic units with a selector coupled to said input terminals and programmable to selectively couple input data from either said data inputs or output terminals of one or more other computational units to said computational unit;
• providing an array of programmable interconnects interconnecting said data inputs of said matrix array and said output terminals of each of said logic units with input terminals of others of said logic units;
• and
• operating each of said logic units and each of said selectors and said array of programmable interconnects on a clocked basis such Boolean functionality is determined during each clock cycle.