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AssigneeInternational Business Machines Corporation
InventorsJeanne Bickford, Markus Buehler, Jason D. Hibbeler, Juergen Koehl
Estimating the term…
Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For example, the method considers the test yield impact of sensitivity to library element to library element shorts and the test yield impact of sensitivity to wiring faults. The disclosed method further allows die size growth to be traded off against the use of library elements with higher test yield in order to provide an optimal design solution. Thus, the method may be used to modify library element selection so as to optimize test yield. Lastly, the method further repeats itself at key design checkpoints to revalidate initial test yield (and cost) assumptions made when the product was quoted to a customer. Thus, the method provides increased accuracy of test yield estimate from initial sizing through design and further allows designs to be modified to improve test yield.
A method for estimating a test yield for a semiconductor product, said method comprising:
A method for estimating test yields for a semiconductor product, said method comprising:
A program storage device readable by computer and tangibly embodying a program of instructions executable by said computer to perform a method of estimating a test yield for a semiconductor product, said method comprising:
Dependencies are inferred from the claim text.