Selection of cells from a multiple threshold voltage cell library for optimized mapping to a multi-vt circuit

A method to select circuit cells for use in optimization of an integrated circuit design from among a plurality of circuit cells within a cell library, the method comprising:

• obtaining from the cell library a power dissipation value for each cell of the plurality that is indicative of the cell's power dissipation;
• obtaining from the cell library a slew sensitivity for each cell of the plurality;
• producing a value for each cell of the plurality that is indicative of the cell's threshold voltage, using a power dissipation value obtained for the cell and using a slew sensitivity value obtained for the cell;
• ordering the cells of the priority based upon the produced values;
• identifying a difference between values of a pair of adjacent cells within the ordering of the cells that meets the threshold;
• and
• designating a cut point between the pair of adjacent cells.

A method to select circuit cells for use in optimization of an integrated circuit design from among a plurality of circuit cells within a cell library, the method comprising:

• obtaining a value for each cell of the plurality that is indicative of at least the cell's power dissipation and the cell's rate of output voltage change;
• ordering the cells of the plurality based upon the obtained values;
• identifying a difference in values of cells of a first pair of proximate cells in the ordering that meet a threshold;
• identifying a difference in values of cells of a second pair of proximate cells in the ordering that meet a threshold;
• providing a cut point selection rule;
• and
• applying the cut point selection rule to select a cut point within the ordering adjacent either the first pair of cells or adjacent the second pair of cells.

A system comprising a processor, storage medium, and communication bus coupling the processor and the storage medium wherein the storage medium is encoded with computer program code to cause the to perform a method to select circuit cells for use in optimization of an integrated circuit design from among a plurality of circuit cells within a cell library, the method including:

• obtaining a value for each cell of the plurality that is indicative of at least the cell's power dissipation and the cell's rate of output voltage change;
• ordering the cells of the plurality based upon the obtained values;
• identifying a difference in values of cells of a first pair of proximate cells in the ordering that meet a threshold;
• identifying a difference in values of cells of a second pair of proximate cells in the ordering that meet a threshold;
• providing a cut point selection rule;
• and
• applying the cut point selection rule to select a cut point within the ordering adjacent either the first pair of cells or adjacent the second pair of cells.