Semiconductor testing system

A semiconductor testing system comprising:

• a pattern generator for generating pattern signals for use in testing a device under test;
• serial converters for executing serial conversion of the pattern signals generated by the pattern generator, respectively;
• transmission paths for transmitting the pattern signals subjected to the serial conversion by the serial converters, respectively;
• parallel converters for executing parallel conversion of the pattern signals transmitted via the respective transmission paths;
• a plurality of memories for allocating the respective pattern signals subjected to the parallel conversion executed by the parallel converters on the basis of every address to be subsequently stored therein;
• a start address detection unit for detecting a start address corresponding to a reading start position of the pattern signal at the time of testing from among a plurality of addresses of the memory out of each of the memories;
• and
• a pattern output unit for starting to read the respective pattern signals from the start address of each of the plurality of the memories, detected by the start address detection unit, against each of the plurality of the memories, to thereby output the respective pattern signals to the device under test.

A semiconductor testing system comprising:

• a pattern generator for generating pattern signals for use in testing a device under test;
• first optical converters for converting the pattern signals generated by the pattern generator, respectively, from electrical signals to optical signals;
• optical transmission paths for transmitting the optical signals converted by first optical converters, respectively;
• second optical converters for converting the optical signals transmitted via the optical transmission paths into pattern signals as voltage signals, respectively;
• a plurality of memories for allocating the respective pattern signals converted by the second optical converters on an address-by address basis to be subsequently stored therein;
• a start address detection unit for detecting a start address corresponding to a reading start position of the pattern signal at the time of testing from among a plurality of addresses of the memory out of each of the memories;
• and
• a pattern output unit for starting to read the respective pattern signals from the start address of each of the plurality of the memories, detected by the start address detection unit, against each of the plurality of the memories, to thereby output the respective pattern signals to the device under test.