Testing Hardware Components To Detect Hardware Failures

A method for testing one or more hardware components, the method comprising:

• generating, at a test pattern injector, a plurality of unique test patterns for a plurality of verification paths, each verification path passing through one or more hardware components, a test pattern generated to test one or more hardware features of the one or more hardware components of a corresponding verification path;
• injecting the test patterns into the corresponding verification paths;
• establishing, at a test pattern detector, a plurality of expected test patterns, an expected test pattern matching an injected test pattern of a corresponding verification path;
• receiving, at the test pattern detector, the test patterns from the verification paths;
• and
• for each corresponding verification path, determining whether the received test pattern matches the expected test pattern.

A system for testing one or more hardware components, the system comprising:

• a test pattern injector coupled to a plurality of verification paths, each verification path passing through one or more hardware components, the test pattern injector configured to:
• generate a plurality of unique test patterns, the test pattern injector comprising a Linear Feedback Shift Register (LFSR) configured to generate the plurality of unique test patterns, a test pattern generated to test one or more hardware features of the one or more hardware components of a corresponding verification path;
• and
• inject the test patterns into the corresponding verification paths by:
• detecting a plurality of selected test timeslots of a frame;
• and
• injecting a test pattern into the test timeslots;
• and
• a test pattern detector coupled to the verification paths, the test pattern detector configured to:
• establish a plurality of expected test patterns, an expected test pattern matching an injected test pattern of a corresponding verification path;
• receive the test patterns from the verification paths;
• for each corresponding verification path, determine whether the received test pattern matches the expected test pattern by:
• determining that a plurality of bits of the received test pattern are the same as a plurality of bits of the expected test pattern;
• provide a notification if the received test pattern does not match the expected test pattern;
• determine that a number of hardware errors exceeds a threshold;
• and
• provide a hard failure notification in response to the determination.