Method and System for Dependency Tracking and Flush Recovery for an Out-Of-Order Microprocessor

A processor, comprising:

• instruction sequencing logic that fetches an instruction sequence for execution, said instruction sequence including a first instruction indicating an update to a particular logical register among a plurality of logical registers and a previous second instruction also indicating an update to the particular logical register;
• a register file including a plurality of physical registers;
• mapping logic that maps said particular logical register to a physical register among the plurality of physical registers within the register file;
• a last definition (DEF) data structure that records an identifier of the first instruction as the most recent instruction in the instruction sequence that defines contents of the particular logical register;
• a next DEF data structure that records the identifier of the first instruction in association with an identifier of the previous second instruction;
• a recovery data structure indicating which of the instructions in the instruction sequence updates each of said plurality of logical registers;
• and
• one or more execution units coupled to the register file and the instruction sequencing logic, wherein said one or more execution units execute the instruction sequence and execute at least some of the instructions in the instruction sequence speculatively;
• wherein the instruction sequencing logic, responsive to misspeculation during execution of the instruction sequence, causes a recovery operation to be performed to place the identifier of the second instruction in the last DEF data structure by reference to said next DEF data structure and said recovery data structure.