System, Method and Software Application for the Generation of Verification Programs
AssigneeMIPS Technologies, Inc.
InventorJames H. Robinson
Life of this patent
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Abstract
A system, method and software application according to the present invention creates complex, interesting, self checking and sturdy verification programs. A self-checking random verification program automatically generates appropriate register and memory reference values, inserts checkpoints and gathers and reports results to test CPU designs. With appropriate templates and simulator, the SRVP framework is largely independent of the CPU architecture and can be utilized to generate randomly generated self-checking verification programs for any CPU architecture and any CPU instruction set.
Claims34
A method for the generation of a verification program for a central processing unit (CPU), comprising randomly generating at least one instruction executable on the CPU, providing the randomly generated instruction to a CPU simulator, whereby the simulator returns both a status of the CPU after the instruction has been executed and a suggestion for change of a prior state of the CPU to modify the effect of the at least one instruction.
A system for the generation of a verification program for a CPU, comprising a generator arranged to generate at least one instruction executable on the CPU, and a simulator arranged to receive the randomly generated instruction, wherein the simulator returns a status of the CPU after the instruction has been executed and a suggestion for change of a prior state of the CPU to modify the effect of the at least one instruction.
A randomly generated program arranged to verify the operation of a CPU, comprising at least one randomly generated instruction and at least one checkpoint arranged to verify the status of the CPU once the randomly generated instruction has been executed.
A method for verifying the architecture of a CPU comprising randomly generating a plurality of executable instructions that include at least one load instruction or one store instruction that access a random value in a base register to determine the memory location for the load or store operation wherein:
- if a physical address (PA) is being read from for the first time, inserting code to initialize the memory location at the physical address to a known value;
- if a virtual address (VA) is mapped by a translation lookaside buffer (TLB), and there is no corresponding valid entry in the TLB at the time the instruction is executed, inserting code in a prior checkpoint to populate the TLB, and mapping the load to an available PA;
- selecting an immediate offset value in a load or store instruction to align the computed VA;
- and
- if the VA is unmapped, discarding the load instruction if the PA is in a region of memory otherwise required by the test.
Dependencies are inferred from the claim text.