Control of cache transactions
AssigneeArm Limited
InventorSimon John Craske
Life of this patent
Estimating the term…
Abstract
A cache memory circuit is provided for use in a data processing apparatus. The cache has a memory array and circuitry for receiving both a transaction input signal and a priority input signal. The priority input signal provides priority information with regard to one or more of the cache transactions received in the transaction input signal. A cache controller is provided for servicing the cache transactions. The cache controller is responsive to the priority input signal to control servicing for at least one of the cache transactions in dependence upon the priority information.
Claims24
A cache comprising:
- a cache memory array having a plurality of cache lines for storing cache entries;
- circuitry for receiving both a transaction input signal comprising a plurality of cache transactions for servicing by said cache and a priority input signal providing priority information with regard to at least one of said cache transactions;
- a cache controller for controlling servicing of said cache transactions;
- wherein said cache controller is responsive to said priority input signal to control servicing of at least one of said plurality of cache transactions in dependence upon said priority information.
A data processing apparatus comprising a priority signal generator for generating a priority signal providing priority information with regard to at least one cache transaction and for supplying said priority information to a cache.
A data processing apparatus comprising:
- a cache memory array having a plurality of cache lines for storing cache entries;
- circuitry for receiving both a transaction input signal comprising a plurality of cache transactions for servicing by said cache and a priority input signal providing priority information with regard to at least one of said cache transactions;
- a cache controller for controlling servicing of said cache transactions;
- wherein said cache controller is responsive to said priority input signal to control servicing of at least one of said plurality of cache transactions in dependence upon said priority information.;
- and
- a priority signal generator for generating said priority signal and supplying said priority signal to said priority signal input of said cache.
A data processing method comprising the steps of:
- receiving at a cache a plurality of cache transactions for servicing by said cache;
- receiving at a cache a priority signal providing priority information with regard to at least one of said cache transactions;
- controlling servicing of at least one of said plurality of cache transactions in dependence upon said priority information.
A cache memory comprising:
- a memory array comprising a plurality of cache lines each having a plurality data storage locations;
- a valid data memory adapted to store valid data representing whether or not data stored in said memory array is valid;
- wherein said valid data represents validity of data corresponding to portions of said cache lines.
Dependencies are inferred from the claim text.