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US 2008/0189479 A1Published application
Device, system and method for controlling memory operations
AssigneeSigmatel, Inc.
InventorsBryan Cope, Tauseef Rab, David Cureton Baker
Life of this patent
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Abstract
A device, system and method for controlling memory operations are disclosed. In an embodiment, data is received at one of multiple slave devices in an integrated circuit. The data is received from at least one bus in a multiple layer bus and is provided to a memory controller. The data is stored in a selected one of multiple memory banks. The memory banks are interleaved such that a first memory address resides on a first memory bank and a next memory address resides on a second memory bank.
Claims27
An integrated circuit comprising:
- a first data bus;
- a second data bus;
- a memory controller coupled to the first data bus and the second data bus;
- a first memory bank coupled to the memory controller;
- a second memory bank coupled to the memory controller;
- wherein the memory controller further comprises logic to allow a first data operation from the first data bus to be performed at one of the first memory bank and the second memory bank and to simultaneously allow a second data operation from the second data bus to be performed at the other of the first memory bank and the second memory bank;
- and
- wherein the first memory bank and the second memory bank are interleaved such that consecutive memory addresses reside on different memory banks.
5 more elements
A method comprising:
- receiving data at one of multiple slave devices in an integrated circuit, the data being received from at least one bus in a multiple layer bus;
- providing the data to a memory controller;
- selecting one of multiple memory banks as a selected memory bank to store the data, wherein the memory banks are interleaved such that a first memory address resides on a first memory bank and a next memory address resides on a second memory bank;
- and
- storing the data in the selected memory bank.
2 more elements
A device comprising:
- a memory controller;
- a first data bus of a multi-layer data bus coupled to the memory controller;
- a second data bus of the multi-layer data bus coupled to the memory controller;
- a first memory slave coupled to the first data bus and the memory controller;
- a second memory slave coupled to the second data bus and the memory controller;
- a first memory bank coupled to a first data output of the memory controller;
- a second memory bank coupled to a second data output of the memory controller;
- and
- wherein the first memory bank and the second memory bank are interleaved.
6 more elements
Dependencies are inferred from the claim text.