Memory device, memory controller and memory system

A semiconductor integrated circuit that integrates circuits on a single semiconductor substrate, comprising:

• a plurality of banks which are assigned to different bank address each other, each of the bank having a plurality of word lines connected to plural memory cells, said plurality of word line being assigned to different row address each other;
• a multi-bank activation control portion which activates a bank assigned to bank address being identical with the input bank address in response to the bank address input with a first operation code, and activates at least one other bank assigned to bank address being different from the input bank address based on multi-bank information;
• and
• a row address calculation portion which generates row address for each activated bank in response to input row address.

A semiconductor integrated circuit that integrates circuits on a single semiconductor substrate, comprising:

• a plurality of data output terminals;
• a plurality of banks which are assigned to different bank address each other, each of the bank having a plurality of word lines assigned to different row address each other, wherein a plurality of memory cells connected to each word line include a plurality of memory unit areas, the memory unit areas being assigned to different column address each other;
• a multi-bank activation control portion which activates a bank assigned to bank address being identical with the input bank address in response to the bank address input with a first operation code, and activates at least one other bank assigned to bank address being not identical with the input bank address based on multi-bank information;
• a row address calculation portion which generates row address for each activated bank in response to input row address;
• a row decoder which activates a word line based on row address generated by the row address calculation portion;
• and
• a control portion which, based on input column address and combination information, output data from plural memory unit areas that is connected to the activated word line to the plural data output terminals in parallel.