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US 2008/0189346 A1Published application
Method for realizing finite field divider architecture
OwnerJau-Yet WU, Hsie-Chia Changinventors
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Abstract
A method for realizing a finite field divider architecture is proposed, in which all standard basis of a divider are transformed into the composite field basis, and the circuit is realized using subfield multiplier, squarer, adder and lookup table over this composite field. The user can finish a division operation within one clock cycle and accomplish the requirement of low complexity. In many finite field operations, divider circuits like this are very helpful to RS/BCH decoders or ECC/Security processors.
Claims8
A method for realizing a finite field divider architecture comprising the steps of:
- transforming all standard basis of division operation with more bits into a plurality of composite field basis with less bits;
- using a plurality of operation units with shorter data paths over said composite field to finish a critical path and replace said division operation with a longer data path;
- and
- transforming result into the standard basis to complete a divider.
1 more element
Dependencies are inferred from the claim text.