Semiconductor device
AssigneeNEC Electronics Corporation
InventorTakayuki Nagai
Life of this patent
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Abstract
The invention provides a semiconductor apparatus capable of achieving a device having a snap-back resisting pressure of about 5 to 10 V by a self-aligning process. The semiconductor apparatus includes two or more sub-gates placed next to a main gate at a predetermined interval, and low concentration layers placed continuously from the ends of source/drain layers to near the end of the main gate, having a potential type same as that of the source/drain layers, and having an impurity concentration lower than that of the source/drain layers.
Claims18
A method of forming a MOS transistor, comprising:
- forming a conductive film over a semiconductor substrate;
- selectively removing said film to leave a continuous pattern of said film having a main gate portion, a sub-gate portion and a connection portion, said main gate portion and said sub-gate portion being adjacent to each other with a space therebetween where said film was removed;
- forming a source/drain region on said substrate;
- and
- forming an impurity diffusion region placed continuously from the end of said source/drain region to near the end of said main gate under said sub-gate, said impurity region having a conductivity type which is the same as that of said source/drain region and having an impurity concentration lower than that of said source/drain region.
A method of forming a MOS transistor, comprising:
- forming a semiconductor substrate of a first conductivity type;
- forming an element isolation region on said semiconductor substrate to define an element formation region;
- forming a main gate and at least one sub-gate on said element formation region, said at least one sub-gate being adjacent to said main gate, said at least one sub-gate and said main gate being formed from a single unitary conductive element so that the main gate and the at least one sub-gate are in direct contact at a first portion and are separated at a second portion in a same plane;
- forming at least one source/drain region of a second conductivity type between said sub gate and said element isolation region, said second conductivity type being different from said first conductivity type;
- and
- forming at least one impurity diffusion region of said second conductivity type between said source/drain region and said main gate under said sub-gate, said impurity diffusion region having an impurity concentration lower than that of said source/drain region.
Dependencies are inferred from the claim text.