Methods for operating and fabricating a semiconductor device having a buried guard ring structure
AssigneeSilicon Space Technology Corporation
InventorWesley H. Morris
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Abstract
Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
Claims28
A method comprising:
- exposing an operating semiconductor device to ionizing radiation, and thereby generate charge within a substrate region;
- collecting the charge onto a buried layer formed within the substrate region and below at least a portion of a first well and a second well, each of said first and second wells having a respective transistor therein;
- shunting the collected charge from the buried layer to a surface terminal by way of a vertical conductive path through the substrate region and the first well, said conductive path comprising a conductive region disposed between the buried layer and the surface terminal, said conductive path having a higher conductance than otherwise would be provided by the first well and the substrate region in the absence of said conductive region;
- dispersing the collected charge from the surface terminal into a voltage source operably coupled to the surface terminal.
A method for making a radiation-hardened integrated circuit (RHIC) product, said method comprising:
- forming a first well of a first conductivity type in a substrate region of a first substrate impurity concentration and of the first conductivity type;
- forming a drain region and a source region for a first transistor within the first well;
- forming a second well of a second conductivity type opposite the first conductivity type;
- forming a buried layer having the first conductivity type and having a buried layer impurity concentration greater than the first substrate impurity concentration, said buried layer disposed within the substrate below the first well and extending continuously beneath the drain and source regions of the first transistor;
- and
- forming a conductive region disposed between the buried layer and one of a first well contact region and a substrate surface terminal within the first well, said conductive region having a smaller lateral extent than that of the first well, and providing a higher conductance between the buried layer and said one of the first well contact region and the substrate surface terminal than a conductance that otherwise would be provided by the first well and the substrate region in the absence of said conductive region.
Dependencies are inferred from the claim text.