Semiconductor devices with dual-metal gate structures and fabrication methods thereof

A method for fabricating a CMOS device with dual-metal gate structures, comprising:

• providing a semiconductor substrate with a first doped region and a second doped region separated by an insulation layer;
• forming an interfacial layer on the semiconductor substrate;
• forming a high-k dielectric layer on the interfacial layer;
• forming a first metal layer on the high-k dielectric layer;
• forming a metal insertion layer on the first metal layer;
• patterning the metal insertion layer, the first metal layer, the high-k dielectric layer, and the interfacial layer exposing the second doped region of the semiconductor substrate;
• conformably forming a second metal layer on the metal insertion layer and the second doped region of the semiconductor substrate;
• forming a polysilicon layer on the second metal layer;
• patterning a first metal gate stack and a second metal gate stack on the first and the second doped regions of the semiconductor substrate;
• forming a sealing layer on sidewalls of the first gate stack and the second gate stack.