Method of fabricating chip package structure
AssigneeChipMOS Technologies (Bermuda) Ltd.
InventorsJie-Hung Chiou, Yong-Chao Qiao, Yan-Yi Wu
Life of this patent
Estimating the term…
Loading patent…
AssigneeChipMOS Technologies (Bermuda) Ltd.
InventorsJie-Hung Chiou, Yong-Chao Qiao, Yan-Yi Wu
Estimating the term…
A method of fabricating a chip package structure includes the steps of providing a lead frame having a die pad, plural leads and at least one structure enhancement element. A chip is then disposed on the die pad and plural bonding wires are formed to electrically connect the chip to the leads. Then, an upper encapsulant and a first lower encapsulant are formed on an upper surface and a lower surface of the lead frame, respectively. The first lower encapsulant has plural concaves to expose the structure enhancement element. Finally, the structure enhancement element is etched with use of the first lower encapsulant as an etching mask until the die pad and one of the leads connected by the structure enhancement element, or two of the adjacent leads connected thereby are electrically insulated.
A method of fabricating a chip package structure, comprising:
A method of fabricating a chip package structure, comprising:
Dependencies are inferred from the claim text.