Network-On-Chip Environment and Method for Reduction of Latency

Abstract

The invention relates to an integrated circuit comprising a plurality of processing modules (IP) and a network (NoC) arranged for coupling processing modules (IP), comprising: the processing module (IP) includes an associated network interface (NI) which is provided for transmitting data to the network (NoC) supplied by the associated processing module and for receiving data from the network (NoC) destined for the associated processing module, wherein the data transmission between processing modules (IP) operates based on time division multiple access (TDMA) using time slots (S) and contention free transmission by using channels (a-d); each network interface (NI) includes a slot table (ST) for storing an allocation of a time slot to a certain channel (a-d), wherein at least a part of the time slots (0-9) allocated to channels (a-d) originated from the same network interface (NI) are shared for transmission of data of the set of channels (a-d). The invention uses the idea to utilize all or at least a part of slots of channels (a-d) in common, which are originating from the same network interface (NI). This will at first reduce the latency of such channels (a-d). Additionally the sizes of the slot tables (ST) in all network components (NI, R1 1-R44) are reduced drastically.

Dependencies are inferred from the claim text.