Wireless Communication Device With Physical-Layer Reconfigurable Processing Engines

Processing circuitry for a wireless communication device comprising:

• two or more reconfigurable processing engines;
• and
• a processing unit to perform high-latency operations and to reconfigure the two or more reconfigurable processing engines with run-time reconfigurators and to control the two or more reconfigurable processing engines via state registers,
• wherein a first of the reconfigurable processing engines performs low-latency operations on complex baseband signals including signal detection, frequency correction and Fourier transform operations to generate soft-bit vectors, the first reconfigurable processing engine being reconfigured by the processing unit for separately performing each of the low-latency operations, and
• wherein a second of the reconfigurable processing engines is configured to perform decoding operations on the soft-bit vectors, the soft-bit vectors being received from the first reconfigurable processing engine over a high-speed data path inaccessible by the processing unit.

A method comprising:

• performing high-latency operations in a processing unit;
• and
• reconfiguring two or more reconfigurable processing engines with run-time reconfigurators and controlling the two or more reconfigurable processing engines via state registers;
• configuring a first of the reconfigurable processing engines to perform low-latency operations on complex baseband signals, the low-latency operations comprising signal detection, frequency correction and Fourier transform operations to generate soft-bit vectors, the first reconfigurable processing engine being reconfigured by the processing unit for separately performing each of the low-latency operations;
• configuring a second of the reconfigurable processing engines to perform decoding operations on the soft-bit vectors;
• and
• receiving the soft-bit vectors from the first reconfigurable processing engine over a high-speed data path inaccessible by the processing unit.

A system comprising:

• a substantially omnidirectional antenna;
• front-end circuitry to generate baseband samples from signals received through the antenna;
• a first reconfigurable processing engine for configuration by a processing unit to perform a plurality of baseband processing operations on the baseband samples, the processing unit to reconfigure the first reconfigurable processing engine for performing each of the baseband processing operations after completion of a prior one of the baseband processing operations;
• and
• a second reconfigurable processing engine for configuration by the processing unit to perform decoding operations on output data generated by the first reconfigurable processing engine.