Circuit for use in a multiple block memory

A memory, comprising:

• a first memory block, comprising a first memory cell coupled to a first memory data line;
• a second memory block, comprising a second memory cell coupled to a second memory data line;
• a latch, having a first terminal and a second terminal;
• a first N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to a power supply voltage, and having a control electrode coupled to the first memory data line;
• and
• a second N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to the power supply voltage, and having a control electrode coupled to the second memory data line.

A method for multiplexing in a memory, the method comprising:

• providing a first memory block;
• providing a second memory block;
• providing a first pair of differential data outputs from the first memory block;
• providing a second pair of differential data outputs from the second memory block;
• and
• multiplexing the first pair of differential data outputs and the second pair of differential data outputs using a plurality of common-drain connected N-channel transistors to provide an output.