Elastic Power for Read and Write Margins

A memory device comprising:

• a first power supply line;
• a second power supply line;
• a static random access memory (SRAM) cell comprising a first logic gate and a second logic gate that are cross-coupled, wherein the first power supply line supplies the first logic gate, and the second power supply line supplies the second logic gate;
• and
• an elastic power header device connected between a reference voltage and each one of the first power supply line and the second power supply line wherein the elastic power header device is configured to provide, during a write operation of the first SRAM cell, different power supply levels on the first power supply line and the second power supply line and is configured to provide, during a read operation, a first resistance in the first power supply line and a second resistance in the second power supply line.

An elastic power header device for providing a first power supply line and a second power supply line in a split power fashion to a memory device, comprising:

• a first conductive path, coupled between a reference voltage and both the first power supply line and the second power supply line, configured to provide a first power supply level difference between the reference voltage and each one of the first power supply line and the second power supply line;
• a second conductive path, coupled between the reference voltage and the first power supply line;
• a third conductive path, coupled between the reference voltage and the second power supply line, wherein, in response to a read operation, a resistance in a selected one of the second conductive path or the third conductive path is kept within a predetermined range of values during a write operation to provide a power supply level difference between the first power supply line and the second power supply line;
• a fourth conductive path, coupled between the reference voltage and the first power supply line;
• and
• a fifth conductive path, coupled between the reference voltage and the second power supply line wherein, in response to a write operation, the resistance in a selected one of the fourth and the fifth conductive paths is varied to provide a resistance.

A computer-readable medium that includes a description of a circuit that implements an elastic power header device which includes a first power supply line and a second power supply line organized in a split power fashion in a memory device, where the circuit is adapted for use with a processor that executes operations that represent instructions, the instructions comprising:

• configuring a first conductive path coupled between a reference voltage and both the first power supply line and the second power supply line, configured to provide a first voltage between the reference voltage and each one of the first power supply line and the second power supply line;
• configuring a second conductive path, coupled between the reference voltage and the first power supply line;
• configuring a third conductive path, coupled between the reference voltage and the second power supply line, wherein, in response to a read operation, a resistance in a selected one of the second conductive path or the third conductive path is kept within a predetermined range of values during a write operation to provide a power supply level difference between the first power supply line and the second power supply line;
• configuring a fourth conductive path, coupled between the reference voltage and the first power supply line to provide a resistance in the first power supply line in response to a write operation;
• and
• configuring a fifth conductive path, coupled between the reference voltage and the second power supply line to provide the resistance in the second power supply line in response to a write operation.

A computer readable medium that includes a description of a memory device, where the memory device comprises:

• a first power supply line;
• a second power supply line;
• a static random access memory (SRAM) cell comprising a first logic gate and a second logic gate that are cross-coupled, wherein the first power supply line supplies the first logic gate, and the second power supply line supplies the second logic gate;
• and
• an elastic power header device connected between the reference voltage and each one of the first power supply line and the second power supply line wherein the elastic power header device is configured to provide, during a write operation of the first SRAM cell, different power supply levels on the first power supply line and the second power supply line and is configured to provide, during a read operation, a first resistance in the first power supply line and a second resistance in the second power supply line.

A memory device comprising:

• means for providing a reference voltage;
• means for configuring a first power supply line and a second power supply line, and means for connecting a static random access memory (SRAM) cell comprising a first logic gate and a second logic gate that are cross-coupled, wherein the first power supply line supplies the first logic gate, and the second power supply line supplies the second logic gates;
• and
• means for providing elastic power connected between the reference voltage and each one of the first power supply line and the second power supply line providing, during a write operation of the first SRAM cell, different power supply levels on the first power supply line and the second power supply line and, during a read operation, providing a first resistance in the first power supply line and a second resistance in the second power supply line.