Semiconductor Memory Devices Having Memory Cell Arrays with Shortened Bitlines

A semiconductor memory device comprising:

• a first memory cell array that comprises a plurality of first wordlines, a plurality of first bitlines, and a plurality of first memory cells that are arranged at the respective intersections of the first wordlines and the first bitlines;
• a second memory cell array that comprises a plurality of second wordlines, a plurality of second bitlines, and a plurality of second memory cells that are arranged at the respective intersections of the second wordlines and the second bitlines;
• a row decoder that is configured to select one of the first and second memory cell arrays in response to a row address;
• a sense amplifier;
• a switch that is configured to connect the sense amplifier to the first memory cell array in response to a first switch enable signal and to connect the sense amplifier to the second memory cell array in response to a second switch enable signal;
• and
• a controller that is configured to activate one of the first and second switch enable signals in response to the row address.