Method for metal bit line arrangement

A method for metal bit line arrangement being applied to a memory, which is a virtual ground array memory and has a plurality of memory cell blocks, each of the memory cell blocks has a plurality of memory cells, a plurality of select transistors and m metal bit lines, wherein m is a positive integer, the method comprising the steps of:

• selecting one of the memory cells as a target memory cell, wherein when the target memory cell is being read, the metal bit line electrically connected to a drain of the target memory cell is defined as a drain metal bit line, and the metal bit line electrically connected to a source of the target memory cell is defined as a source metal bit line;
• performing a classification of whether the other metal bit lines are charged up when the target memory cell is being read;
• and
• arranging the m metal bit lines such that a charged up metal bit lines is not adjacent to the source metal bit line.