Non-volatile semiconductor memory device

A non-volatile semiconductor memory device comprising:

• a P type non-volatile memory cell formed in an N type well, said P type non-volatile memory cell including a source, a drain, a charge accumulation layer and a control gate;
• a sub-bit line connected to said drain of said P type non-volatile memory cell;
• an N type selection transistor including a source, a drain and a control gate, said drain of said N type selection transistor being connected to said sub-bit line;
• and
• a well bias circuit to bias said N type well with a first voltage so that said sub-bit line is floated and boosted to a program inhibit voltage by a capacitive coupling between said N type well and said drain of said P type non-volatile memory cell.

A non-volatile semiconductor memory device comprising:

• first and second P type non-volatile memory cells each formed in an N type well, each of said first and second P type non-volatile memory cells including a source, a drain, a charge accumulation layer and a control gate;
• a sub-bit line connected to said drain of said first P type non-volatile memory cell and said drain of said second P type non-volatile memory cell;
• an N type selection transistor including a source, a drain and a control gate, said drain of said N type selection transistor being connected to said sub-bit line;
• and
• a source line connected to said source of said first P type non-volatile memory cell and said source of said second P type non-volatile memory cell;
• and
• a source line bias circuit to bias said source line with a program inhibit voltage so that said sub-bit line is biased to said program inhibit voltage by turning on said second P type non-volatile memory cell.

A non-volatile semiconductor memory device comprising:

• a P type non-volatile memory cell formed in an N type well, said P type non-volatile memory cell including a source, a drain, a charge accumulation layer and a control gate;
• a sub-bit line connected to said drain of said P type non-volatile memory cell;
• an N type selection transistor including a source, a drain and a control gate, said drain of said N type selection transistor being connected to said sub-bit line;
• a source line;
• a source line bias circuit to bias said source line with a program inhibit voltage;
• and
• a P type pre-charging transistor formed in said N type well for connecting said source line and said sub-bit line to pre-charge said sub-bit line to said program inhibit voltage and for disconnecting said sub-bit line from said source line so that said sub-bit line is floated.

A non-volatile semiconductor memory device comprising:

• an N type well for a plurality of memory cells formed within, said N type well being biased by an N well bias voltage though a first number (N1) of contacts;
• and
• a P type well for a plurality of selection transistors formed within, said P type well being biased by a P well bias voltage though a second number (N2) of contacts;
• wherein the first number (N1) is greater than the second number (N2).

A non-volatile semiconductor memory device comprising:

• a first memory block having a plurality of P type memory cells arranged in matrix shape formed in a first N type well;
• a second memory block having a plurality of P type memory cells arranged in matrix shape formed in a second N type well;
• and
• a plurality of selection transistors formed between said first N type well and said second N type well.

A non-volatile semiconductor memory device comprising:

• a memory block having a plurality of P type memory cells arranged in matrix formed in an N type well;
• a plurality of sub bit lines each of said sub bit lines being connected to corresponding P type memory cells in a column of said matrix;
• and
• a plurality of pre-charging transistors formed in said N type well, each of said pre-charging transistors pre-charges corresponding one of said sub bit lines with a program inhibit voltage.