Nor architecture memory and operation method thereof
AssigneeMacronix International Co., Ltd.
InventorYung-Feng Lin
Life of this patent
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Abstract
An operation method of a NOR architecture memory includes the following steps. First, a target word line is selected. Next, an initial enable voltage is applied to the target word line to charge the target word line. Then, the initial enable voltage is switched to a target voltage after a pre-charge time to make the target word line be charged to the target voltage. The initial enable voltage is higher than the target voltage. The pre-charge time corresponds to the initial enable voltage and the target voltage.
Claims14
An operation method for a NOR architecture memory, the method comprising the steps of:
- selecting a target word line;
- applying an initial enable voltage to the target word line to charge the target word line;
- and
- switching the initial enable voltage, which is higher than a target voltage, to the target voltage after a pre-charge time to make the target word line be charged to the target voltage,
- wherein the pre-charge time corresponds to the initial enable voltage and the target voltage.
An NOR architecture memory, comprising:
- a NOR architecture memory cell array having a plurality of memory cells arranged in an array having m rows and n columns, m and n being positive integers;
- m word lines respectively corresponding to the m rows of memory cells, wherein each of the word lines is coupled to n gates of the corresponding row of memory cells;
- a row decoder for selecting one of the word lines as a target word line;
- and
- a control circuit, which is coupled to the row decoder, applies an initial enable voltage to the target word line to charge the target word line, and then switches the initial enable voltage to a target voltage after a pre-charge time to make the target word line be charged to the target voltage, wherein the initial enable voltage is higher than the target voltage.
Dependencies are inferred from the claim text.