Advanced MRAM design

An integrated circuit memory chip, comprising:

• a first memory cell array comprising an array of high-speed magnetic memory cells, wherein each of the high-speed magnetic memory cells comprises one switching device for one magnetoresistive stack;
• a second memory cell array adjacent to the first memory cell array, the second memory cell array comprising an array of high-density magnetic memory cells, wherein each of the high-density magnetic memory cells comprises one switching device per at least two magnetoresistive stacks;
• first array logic for use with the magnetic memory cells in the high-speed memory array;
• second control logic for use with the magnetic memory cells in the high-density memory array;
• a first set of conductive lines interfacing the first array logic with the high-speed memory array;
• and
• a second set of conductive lines interfacing the second array logic with the high-density memory array.

An integrated circuit memory chip, comprising:

• a first memory cell array comprising an array of high-speed magnetic memory cells, wherein each of the high-speed magnetic memory cells comprises at least one switching device per one magnetoresistive stack;
• a second memory cell array adjacent to the first memory cell array, the second memory cell array comprising an array of high-density magnetic memory cells, wherein each of the high-density magnetic memory cells comprises one switching device per at least two magnetoresistive stacks;
• array logic for use with the magnetic memory cells in the high-speed memory array and with the magnetic memory cells in the high-density memory array;
• a first set of conductive lines interfacing the array logic with the high-speed memory array;
• and
• a second set of conductive lines interfacing the array logic with the high-density memory array.