Memory cell device and programming methods

A method for programming a memory cell comprising phase change material, the method comprising:

• determining a data value for the memory cell;
• applying a reset pulse if the determined data value is a first data value, the reset pulse having a pulse shape adapted to cause a transition of an active region into an amorphous phase, thereby setting the phase change material to a resistance corresponding to the first data value;
• applying a first pulse pair if the determined data value is a second data value, the first pulse pair comprising a first pulse having a pulse shaped adapted to cause a transition of the active region into an amorphous phase, and a second pulse having a pulse shape adapted to cause of transition of a portion of the active region into a crystalline phase, thereby setting the phase change material to a resistance corresponding to the second data value;
• and
• applying a second pulse pair if the determined data value is a third data value, the second pulse pair comprising a third pulse having a pulse shape adapted to cause a transition of the active region into an amorphous phase, and a fourth pulse having a pulse shape adapted to cause a transition of a portion of the active region into a crystalline phase, thereby setting the phase change material to a resistance corresponding to the third data value.

A memory device comprising:

• a memory cell comprising phase change material;
• and
• bias circuitry adapted to apply a bias arrangement to the memory cell for storing a data value;
• wherein the bias arrangement for storing the data value comprises a pulse pair, the pulse pair including an initial pulse having a pulse shape adapted to preset the phase change material in the memory cell to a normalizing resistance state and a subsequent pulse having a pulse shape adapted to set the phase change material in the memory cell from the normalizing resistance state to a resistance corresponding to the data value.

A memory device comprising:

• a memory cell comprising phase change material;
• and
• bias circuitry adapted to apply a bias arrangement to the memory cell for storing a data value;
• wherein the bias arrangement comprises a reset pulse if the data value is a first data value, the reset pulse having a pulse shape adapted to cause a transition of an active region into an amorphous phase, thereby setting the phase change material to a resistance corresponding to the first data value;
• wherein the bias arrangement comprises a first pulse pair if the data value is a second data value, the first pulse pair comprising a first pulse having a pulse shaped adapted to cause a transition of the active region into an amorphous phase, a second pulse having a pulse shape adapted to cause a transition of a portion of the active region into a crystalline phase, thereby setting the phase change material to a resistance corresponding to the second data value;
• wherein the bias arrangement comprises a second pulse pair if the data value is a third data value, the second pulse pair comprising a third pulse having a pulse shape adapted to cause a transition of the active region into an amorphous phase, and a fourth pulse having a pulse shape adapted to cause a transition of a portion of the active region into a crystalline phase, thereby setting the phase change material to a resistance corresponding to the third data value.