Multilayer chip capacitor

A multilayer chip capacitor comprising:

• a capacitor body formed by laminating a plurality of dielectric layers and having a bottom surface to be mounted on a circuit board;
• a plurality of internal electrodes disposed in perpendicular to the bottom surface in the capacitor body with each of the dielectric layers interposed therebetween;
• a first external electrode of a first polarity formed on a first side surface of the capacitor body to partially extend to the bottom surface;
• a second external electrode of the first polarity formed on a second side surface opposite to the first side surface to partially extend to the bottom surface;
• and
• a third external electrode of a second polarity formed on the bottom surface between the first and second external electrodes,
• wherein a width of the third external electrode is larger than a width of a portion of the first external electrode extending to the bottom surface and a width of a portion of the second external electrode extending to the bottom surface.

A multilayer chip capacitor comprising:

• a capacitor body formed by laminating a plurality of dielectric layers and having a bottom surface to be mounted on a circuit board and first and second side surfaces facing each other;
• a plurality of first-polarity and second-polarity internal electrodes alternately disposed to face each other in the capacitor body with each of the dielectric layers interposed therebetween and disposed in perpendicular to the bottom surface of the capacitor body;
• first and second external electrodes formed on the first and second side surfaces, respectively, to partially extend to the bottom surface and to be electrically connected to the first-polarity internal electrodes;
• and
• a third external electrode formed on the bottom surface between the first and second external electrodes to be connected to the second-polarity internal electrodes,
• wherein two current loops are generated by currents flowing from the first and second external electrodes to the third external electrode.

A multilayer chip capacitor comprising:

• a capacitor body formed by laminating a plurality of dielectric layers and having a bottom surface to be mounted on a circuit board and first and second side surfaces facing each other;
• a plurality of first-polarity and second-polarity internal electrodes alternately disposed to face each other in the capacitor body with each of the dielectric layers interposed therebetween, the first-polarity and second-polarity internal electrodes being disposed in perpendicular to the bottom surface of the capacitor body;
• first and second external electrodes formed on the first and second side surfaces to extend to the bottom surface and to be electrically connected to the first-polarity internal electrodes;
• and
• a third external electrode formed on the bottom surface between the first and second external electrodes to be connected to the second-polarity internal electrodes,
• wherein each of the first-polarity internal electrodes has a first-polarity main portion and a first-polarity lead drawn from the first-polarity main portion to the bottom surface and one side surface to be connected to one of the first and second external electrodes,
• wherein each of the second-polarity internal electrodes has a second-polarity main portion and a second-polarity lead drawn from the second-polarity main portion to the bottom surface to be connected to the third external electrode,
• wherein a distance from the first-polarity main portion to the bottom surface is equal to a distance from the second-polarity main portion to the bottom surface, and
• wherein ESL of 100 pH or less is obtained by adjusting a gap G between adjacent first-polarity lead and the second-polarity lead, a distance M from the first-polarity main portion to the bottom surface, the number N of internal electrodes in the capacitor body, and a lead width ratio W2/W1 of a width W2 of the second-polarity lead to a width W1 of a portion of the first-polarity drawn to the bottom surface.

A multilayer chip capacitor comprising:

• a capacitor body formed by laminating a plurality of dielectric layers and having a bottom surface to be mounted on a circuit board, first and second side surfaces facing each other, and third and fourth side surfaces facing each other;
• a plurality of first-polarity and second-polarity internal electrodes alternately disposed to face each other in the capacitor body with each of the dielectric layers interposed therebetween, the first-polarity and second-polarity internal electrodes being disposed in parallel to the bottom surface of the capacitor body;
• a first external electrode formed on the first side surface to partially extend to the third and fourth side surfaces and to be electrically connected to the first-polarity internal electrodes;
• a second external electrode formed on the second side surface to partially extend to the third and fourth side surfaces and to be electrically connected to the first-polarity internal electrodes;
• and
• a third external electrode formed on the third and fourth side surfaces between the first and second side surfaces to be electrically connected to the second-polarity internal electrodes;
• wherein each of the first-polarity internal electrodes has a first-polarity lead drawn to the third and fourth side surfaces and one of the first and second side surfaces to be connected to one of the first and second external electrodes,
• wherein each of the second-polarity internal electrodes has two second-polarity leads drawn to the third and fourth side surfaces to be connected to the third external electrode, and
• wherein a width ratio of a width of the second-polarity lead to a width of a portion of the first-polarity lead drawn to the third side surface is 1.43 or more.