System on chip including an image processing memory with multiple access

A system on chip (SoC) comprising:

• a plurality of sub-systems, each of the sub-systems including a monitoring unit for checking an operation state of a corresponding sub-system, the sub-systems included in respective power domains;
• a system bus connected to each of the sub-systems;
• an image processing logic block connected to the system bus, the image processing logic block being configured to perform an image processing, the image processing logic block being included in a first power domain different from the power domains of the sub-systems;
• an image memory interface connected to the system bus and the image processing logic block;
• an image processing memory block connected to the image memory interface, the image processing memory block being configured to be used for the image processing, the image memory interface and the image processing memory block being included in a second power domain different from the power domains of the sub-systems and different from the first power domain;
• and
• a power supply unit configured to supply power to the first power domain, the second power domain and power domains of the sub-systems

A system on chip (SoC) comprising:

• a plurality of sub-systems, each of the sub-systems including a monitoring unit for checking an operation state of a corresponding sub-system, the sub-systems included in respective power domains;
• a system bus connected to each of the sub-systems;
• an image processing logic block connected to the system bus, the image processing logic block being configured to perform an image processing, the image processing logic block being included in a first power domain different from the power domains of the sub-systems;
• an image memory interface connected to the system bus and the image processing logic block, the image memory interface for checking an operation state of the image processing logic block;
• an image processing memory block connected to the image memory interface, the image processing memory block being configured to be used for the image processing, the image memory interface and the image processing memory block being included in a second power domain different from the power domains of the sub-systems and different from the first power domain;
• a power supply unit configured to supply power to the first power domain, the second power domain and power domains of the sub-systems;
• and
• a control unit configured to receive operation state information of the sub-systems from each of the monitoring units and receive operation state information of the image processing logic block from the image memory interface to provide a control signal to the power supply unit, the control signal being for performing a power-down operation.