Timing controller, liquid crystal display device having the same, and method of operating a timing controller

A timing controller comprising:

• a first line memory block storing pixel data on an Nth horizontal line of a liquid crystal panel received by a first data transfer frequency, wherein N is a natural number;
• a second line memory block storing pixel data on an (N+1)th horizontal line of the liquid crystal panel received by the first data transfer frequency;
• a selection block, which is connected to input terminals of the first and the second line memory block, outputting pixel data received from an external source to the first line memory block or the second line memory block in response to a line memory selection signal;
• a control unit, connected to output terminals of the first and the second line memory blocks, transferring pixel data output from the first and the second line memory blocks to a frame memory at a second data transfer frequency, converting pixel data output from the frame memory to a predetermined data format, and outputting the converted pixel data;
• a data format conversion unit converting pixel data output from the control unit to a data format corresponding to a driving method of the liquid crystal panel;
• and
• a control signal generator generating a plurality of control signals driving the liquid crystal panel in response to a control signal output from the control unit.

An operating method of a timing controller comprising:

• outputting pixel data received at a selection circuit at a first data transfer frequency to a first line memory block or a second line memory block in response to a line memory selection signal;
• the first line memory block storing pixel data on an Nth, where N is a natural number, horizontal line of a liquid crystal panel among the pixel data received at the first data transfer frequency;
• the second line memory block storing pixel data on an (N+1)th horizontal line of the liquid crystal panel among the pixel data received at the first data transfer frequency;
• and
• transferring pixel data output from the first and the second line memory blocks with an external frame memory at a second data transfer frequency at a control unit, which is connected to an output terminal of the first and the second line memory block respectively.