On-chip electrically alterable resistor

A CMOS IC as in claim 17, further comprising:

• an operational amplifier (op-amp), a reference voltage connected to a first op-amp input and said dynamically variable resistor connected to a second op-amp input;
• a first PFET gated by an output of said op-amp, a drain of said PFET connected to said common resistive load line;
• a second PFET connected gate to drain to the source of said first PFET;
• and
• a third PFET having its gate connected to the gate of said second PFET, the drain of said third PFET being the output of said current source;
• whereby resistance of said dynamically variable resistor is tuned both by switching phases on individual chalcogenide resistors and individually switching said four bit select, said two bit select and said resistance adjust on fourth of said four.

A CMOS IC chip including a current source, said current source comprising:

• an on-chip electrically alterable (EA) resistor;
• an operational amplifier (op-amp), a reference voltage connected to a first op-amp input and said on-chip EA resistor connected to a second op-amp input;
• a first PFET gated by an output of said op-amp, a drain of said PFET connected to said on-chip EA resistor;
• a second PFET connected gate to drain to the source of said first PFET;
• and a third PFET having its gate connected to the gate of said second PFET, the drain of said third PFET being the output of said current source.