Level detector, communication apparatus, and tuner

A level detector comprising:

• a signal input;
• a comparing circuit that generates a signal comprising a plurality of temporally successive pulses each having its width corresponding to the length of a time period during which the strength of an input signal from the input is lower than a second reference value;
• and
• an integrating circuit that outputs a signal having its strength corresponding to an integration value obtained by temporally integrating the strength of the signal generated by the comparing circuit.

A level detector comprising:

• a signal input;
• a first comparing circuit that generates a signal comprising a plurality of temporally successive pulses each having its width corresponding to the length of a time period during which the strength of an input signal from the input is higher than a first reference value;
• a second comparing circuit that generates a signal comprising a plurality of temporally successive pulses each having its width corresponding to the length of a time period during which the strength of the input signal from the input is lower than a second reference value lower than the first reference value;
• an OR circuit that generates a signal having its strength corresponding to the logical sum of the signal generated by the first comparing circuit and the signal generated by the second comparing circuit;
• a pulse width extending circuit that generates a signal in which each pulse contained in the signal generated by the OR circuit has been temporally extended;
• and
• an integrating circuit that outputs a signal having its strength corresponding to an integration value obtained by temporally integrating the strength of the signal generated by the pulse width extending circuit.

A level detector comprising:

• first to n-th signal inputs corresponding to n input signals, where n represents a natural number more than one;
• first to n-th comparing circuits each of which generates a signal comprising a plurality of temporally successive pulses each having its width corresponding to the length of a time period during which the strength of an input signal from the corresponding one of the first to n-th inputs is higher than a first reference value;
• an OR circuit that generates a signal having its strength corresponding to the logical sum of the signals generated by the first to n-th comparing circuits;
• a pulse width extending circuit that generates a signal in which each pulse contained in the signal generated by the OR circuit has been temporally extended;
• and
• an integrating circuit that outputs a signal having its strength corresponding to an integration value obtained by temporally integrating the strength of the signal generated by the pulse width extending circuit.

A communication apparatus comprising:

• an input to which a communication signal is input;
• a comparing circuit that generates a signal comprising a plurality of temporally successive pulses each having its width corresponding to the length of a time period during which the strength of the input signal from the input is higher than a predetermined reference value;
• and
• an integrating circuit that outputs a signal having its strength corresponding to an integration value obtained by temporally integrating the strength of the signal generated by the comparing circuit,
• the apparatus detecting the level of the communication signal on the basis of the output from the integrating circuit.

A tuner comprising:

• an amplifier that amplifies an input signal and then outputs the amplified signal;
• a channel selecting unit that applies a channel selecting process to the signal output from the amplifier;
• a comparing circuit that generates a signal comprising a plurality of pulses each having its width corresponding to the length of a time period during which the strength of the signal channel-selecting-processed by the channel selecting unit is higher than a predetermined reference value;
• an integrating circuit that outputs a signal having its strength corresponding to an integration value obtained by temporally integrating the strength of the signal generated by the comparing circuit;
• and
• a gain controller that decreases the gain of the amplifier in accordance with the degree that the strength of the signal output from the integrating circuit is higher than a desired value;
• and increases the gain of the amplifier in accordance with the degree that the strength of the signal output from the integrating circuit is lower than the desired value.