Circuit and method for reducing pin count of chip
AssigneeRealtek Semiconductor Corp.
InventorMing-Yuh Yeh
Life of this patent
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Abstract
A configured setting circuit and method thereof is disclosed. The configured setting circuit includes a multi-phase clock generator, a plurality of terminals, and a decision circuit. The multi-phase clock generator generates a plurality of multi-phase signals with different phases to be outputted via the terminals. The decision circuit detects a phase difference between the input signal and the reference signal and outputs a configuration data according to the phase difference between the input signal and the reference signal.
Claims20
A circuit for producing a configuration data, comprising:
- a multiple-phase clock generating circuit utilized to generate a plurality of clock signals, wherein phases of the plurality of clock signals are substantially different;
- a plurality of first terminals utilized to output the plurality of clock signals;
- a second terminal utilized to receive a first input signal, in which the first input signal is substantially one of the plurality of clock signals;
- and
- a first decision circuit, coupled to the first terminal, utilized to receive a reference signal, detect a phase difference between the reference signal and the first input signal, and generate a first configuration data of the configuration data according to the phase difference between the reference signal and the first input signal.
A circuit for producing a configuration data, comprising:
- a first terminal utilized to receive a first input signal, wherein the first input clock is one of a plurality of input signals with different phase;
- and
- a first decision circuit, coupled to the first terminal, utilized to receive a reference signal, detect a phase difference between the reference signal and the first input signal, and produce a first configuration signal of the configuration signal according to the phase difference between the reference signal and the first input signal.
A method, comprising:
- providing a reference signal;
- utilizing a first terminal to receive a first input signal, wherein the first input clock is one of a plurality of clock signals with different phase;
- detecting a phase difference between the reference signal and the first input signal to output a first phase difference signal;
- and
- determining a first configuration signal according to the first phase difference signal.
Dependencies are inferred from the claim text.