Circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices
AssigneeProMOS Technologies PTE.LTD.
InventorJohn D. Heightley
Life of this patent
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Abstract
A circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices in which only N-channel current regulating transistors are used in the voltage-controlled inverters and both the rising and falling edges can be adjusted by cascading two such inverters. The potential for cascading of these inverters allows for additional accuracy to be achieved.
Claims34
A duty cycle adjusting circuit comprising:
- first and second cascaded voltage-controlled inverters coupled between a supply voltage source and a reference voltage level, said first voltage-controlled inverter receiving a first control voltage at an input thereof and said second voltage-controlled inverter receiving a second control voltage at an input thereof, said first and second control voltages moving in opposite directions as an output of said circuit diverges from a 50% duty cycle.
A duty cycle adjuster circuit comprising:
- a first voltage-controlled inverter receiving an input clock signal and a first control voltage;
- and
- a second voltage-controlled inverter coupled to an output of said first voltage-controlled inverter and receiving a second control voltage, said second voltage-controlled inverter providing a corrected output clock signal in response to said output of said first voltage-controlled inverter and said second control voltage.
A method for adjusting the duty cycle of an input signal comprising:
- providing first and second series coupled inverters;
- firstly adjusting a propagation delay of a rising edge of said input signal with said first inverter;
- and
- secondly adjusting a propagation delay of a falling edge of said input signal with said second inverter.
A duty cycle adjusting circuit having compensation for self-generated duty cycle error comprising:
- cascade coupled first and second voltage-controlled inverters for coupling between a supply voltage and a reference voltage;
- cascade coupled third and fourth voltage-controlled inverters for coupling between said supply voltage and said reference voltage;
- a first non-voltage-controlled inverter cascaded between an output of said second voltage-controlled inverter and an input of said third voltage-controlled inverter;
- a second non-voltage-controlled inverter cascaded between an output of said fourth voltage-controlled inverter and an output of said circuit;
- said first and fourth voltage-controlled inverters receiving a first control voltage at control inputs thereof and said second and third voltage-controlled inverters receiving a second control voltage a control inputs thereof, said first and second control voltages moving in opposite directions thereof as said output of said circuit diverges from a 50% duty cycle.
Dependencies are inferred from the claim text.