Low frequency detector including common input voltage sensor
AssigneeTexas Instruments Incorporated
InventorsOtani Daijiro, Hisao Ogiwara
Life of this patent
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Abstract
A low frequency detector circuit includes a differential input that is received by an offset comparator circuit. The offset comparator circuit provides respective output signals COMPX and COMPY which can be compared to a generated threshold voltage Vcomp by an E2C (ECL to CMOS) comparators. The outputs of the E2C comparators are used by respective timers to generate fault signals. In addition to detecting low frequency conditions, common voltage conditions can be detected as well and can be distinguished at very high frequency conditions.
Claims14
A low frequency detector for determining whether the frequency of a differential input signal is below a predetermined frequency threshold, comprising:
- an offset comparator circuit for receiving first and second complementary differential input signals and generating a reference threshold voltage and respective first and second output signals, wherein the output signals are less than the reference threshold voltage if the differential input is within a predetermined offset voltage range;
- first and second ECL-to-CMOS comparators for generating status signals, the first ECL-to-CMOS comparator having inputs coupled to the first output signal and the reference threshold voltage signal from the offset comparator circuit and the second ECL-to-CMOS comparator having inputs coupled to the second output signal and the reference threshold voltage signal from the offset comparator circuit;
- and
- first and second timer circuits coupled to the first and second ECL-to-CMOS comparators for generating a fault signal responsive to the status signals from the first and second comparators.
A low frequency detector circuit comprising:
- circuitry for detecting whether a differential input signal, comprising first and second complementary signals, has a frequency below a predetermined threshold frequency;
- and
- circuitry for detecting whether the differential input signal is within a predetermined voltage range.
A method of detecting whether the frequency of a differential input signal is below a predetermined frequency threshold, comprising the steps of:
- receiving the first and second complementary differential input signals;
- generating a reference threshold voltage and respective first and second output signals, wherein the output signals are less than the reference threshold voltage if the differential input is within a predetermined offset range;
- generating status signals with first and second ECL-to-CMOS comparators, the first ECL-to-CMOS comparator having inputs coupled to the first output signal and the reference threshold voltage signal from the offset comparator circuit and the second ECL-to-CMOS comparator having inputs coupled to the second output signal and the reference threshold voltage signal from the offset comparator circuit;
- and
- generating fault signals responsive to the status signals.
Dependencies are inferred from the claim text.