Methods, systems, and computer program products for using direct memory access to initialize a programmable logic device

An integrated circuit (IC) for using direct memory access (DMA) to initialize a programmable logic device (PLD), the IC operably coupled to the PLD, the IC comprising:

• an input/output (I/O) interface, the I/O interface converting a signal format between the IC and the PLD;
• and
• a PLD interface, the PLD interface including:
• a configuration and status register, the configuration and status register adapted to manipulate a control line of the PLD to configure the PLD in a programming mode via the I/O interface;
• a data buffer, the data buffer for temporarily holding PLD programming data received from a DMA control at a DMA speed;
• and
• pacing logic, the pacing logic controlling the speed of transmitting the PLD programming data to a programming port on the PLD via the I/O interface at a PLD programming speed.

A method for initializing a programmable logic device (PLD), the method comprising:

• manipulating a control line of the PLD to configure the PLD in a programming mode;
• selecting a PLD programming data source from at least one of a DMA control and a processor;
• receiving PLD programming data from the selected data source;
• and
• transmitting the PLD programming data to a programming port on the PLD.

A system for using direct memory access (DMA) to initialize a programmable logic device (PLD), the system comprising:

• the PLD including a programming port with a control line, the PLD on an assembly;
• and
• an integrated circuit (IC) operably coupled to the programming port of the PLD, the IC on the assembly, and including:
• an input/output (I/O) interface, the I/O interface converting a signal format between the IC and the PLD;
• and
• a PLD interface, the PLD interface including:
• a configuration and status register, the configuration and status register adapted to manipulate the control line of the programming port of the PLD via the I/O interface;
• a data buffer, the data buffer for temporarily holding PLD programming data received from a DMA control at a DMA speed;
• and
• pacing logic, the pacing logic controlling the speed of transmitting the PLD programming data to the programming port on the PLD via the I/O interface at a PLD programming speed.

A computer program product for supporting using direct memory access (DMA) to initialize a programmable logic device (PLD), the computer program product comprising:

• a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for facilitating a method comprising:
• manipulating a control line of the PLD to configure the PLD in a programming mode;
• receiving PLD programming data from a DMA control at a DMA speed;
• and
• transmitting the PLD programming data to a programming port on the PLD at a PLD programming speed.