US 2008/0185661 A1 · Semiconductor device and method for fabricating the same

Abstract

A first MIS transistor includes: a first gate insulating film formed on a first active region; a first gate electrode formed on the first gate insulating film; first sidewall insulating films formed on side surfaces of the first gate electrode; first source/drain regions formed at outer sides of the first sidewall insulating film in the first active region; a silicide region formed as an upper layer of each of the first source/drain regions; a first underlying insulating film formed over the first active region using ALD so as to cover the first gate electrode, the first insulating films and the silicide region; and a first contact liner film formed on the first underlying insulating film using plasma CVD and made of a stress insulating film for applying a tensile or compressive stress in a gate length direction in a channel region.

Claims13

Dependent claims

A semiconductor device comprising a first MIS transistor formed on a first active region in a semiconductor substrate,

wherein the first MIS transistor comprises:
a first gate insulating film formed on the first active region;
a first gate electrode formed on the first gate insulating film;
first sidewall insulating films formed on side surfaces of the first gate electrode;
first source/drain regions formed at outer sides of the first sidewall insulating film in the first active region;
a silicide region formed as an upper layer of each of the first source/drain regions;
a first underlying insulating film formed over the first active region using ALD so as to cover the first gate electrode, the first insulating films and the silicide region;
and
a first contact liner film formed on the first underlying insulating film using plasma CVD and made of a stress insulating film for applying a tensile or compressive stress in a gate length direction in a channel region.

6 more elements

A method for fabricating a semiconductor device, the method comprising the steps of:

a) forming a first gate insulating film over a first active region in a semiconductor substrate;
b) forming a first gate electrode on the first gate insulating film;
c) forming first sidewall films on side surfaces of the first gate electrode;
d) forming first source/drain regions at outer sides of the first sidewall films in the first active region;
e) forming a silicide region as an upper layer of each of the first source/drain regions;
f) forming a first underlying insulating film over the first active region using ALD so as to cover the first gate electrode, the first insulating films and the silicide region;
and
g) forming a first contact liner film on the first underlying insulating film using plasma CVD and made of a stress insulating film for applying a tensile or compressive stress in a gate length direction in a channel region.

5 more elements

Dependencies are inferred from the claim text.

Semiconductor device and method for fabricating the same

Life of this patent

Semiconductor device and method for fabricating the same

Life of this patent

Abstract

Claims13