Recessed transistor and method of manufacturing the same

A method of manufacturing a recessed transistor, comprising:

• forming an isolation layer to establish an active region and a field region of a substrate;
• forming an upper recess having a first width on a surface portion of the substrate in the active region;
• partially etching the substrate exposed through the upper recess to form a recessed structure having the upper recess and a lower recess in communication with the upper recess and to form an active pin between the lower recess and the isolation layer;
• forming a gate insulation layer on a side surface and a bottom surface of the recessed structure;
• forming a gate electrode on the gate insulation layer in the recessed structure;
• and
• forming source and drain regions in the active region adjacent to the gate electrode.

A method of manufacturing a recessed transistor, comprising:

• forming an upper trench having a first width at a surface portion of a substrate;
• forming a lower trench having a second width less than the first width (w1), wherein the lower trench is in communication with the upper trench;
• filling the upper trench and the lower trench with an isolation layer to establish an active region and a field region of the substrate;
• partially etching the substrate in the active region to form a recessed structure having the upper recess and the lower recess and to form an active pin between the lower recess and the isolation layer;
• forming a gate insulation layer on a side surface and a bottom surface of the recessed structure;
• forming a gate electrode on the gate insulation layer in the recessed structure;
• and
• forming source and drain regions in the active region adjacent to the gate electrode.