RFID tag having non-volatile memory device having floating-gate fets with different source-gate and drain-gate border lengths

A method, comprising:

• storing a value in a field-effect transistor (FET) of a non-volatile memory (NVM) within an RFID tag circuit by performing the following:
• biasing the FET to inject electrons onto a floating gate of the FET;
• differentially and capacitively drawing at least 10% more charge carriers of the floating gate toward a first doped region of the FET than toward a second doped region of the FET;
• flowing charge carriers through a channel region of the FET between the first and second doped regions;
• storing charge of an amount that encodes the value on the floating gate by injecting the electrons onto the floating gate of the FET while the charge carriers flow through the channel region of the biased FET.

A method, comprising:

• forming a non-volatile memory (NVM) device within an RFID tag circuit die by performing the following:
• forming a field-effect transistor (FET) on a substrate, including:
• forming a floating gate over a well region of a substrate;
• and
• forming first and second doped regions in the well region on opposite sides of the floating gate including forming a first border of a first length between the first doped region and the floating gate, and forming a second border of a second length that is less than 90% of the first length between the second doped region and the floating gate;
• and
• forming at least one selective biasing circuit on the substrate, in which the at least one selective biasing circuit is electrically coupled with the FET to apply one or more signals to the FET to store charge of an amount that encodes a value on the floating gate.