Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices

The method of claim 8 further comprising:

• removing said spacers after forming the source region;
• etching the sidewalls of said screening structure so as to reduce a width of the screening structure;
• forming, in cascade, a thin dielectric layer and a conductive layer;
• and
• forming gate structures by etching, in succession, said conductive layer and said thin dielectric layer so that said gate structures are partially overlapped onto said implanted body region insulated from said implanted body region and said source region by thin dielectric portions of said thin dielectric layer, said gate structures being substantially aligned to said implanted source region.

A vertical power MOS device, comprising:

• a semiconductor substrate of a first type of conductivity;
• a semiconductor portion of a second type of conductivity positioned in said semiconductor substrate;
• an implanted body region of the second first type of conductivity positioned within the semiconductor portion;
• a doped source region of the second type of conductivity formed inside said implanted body region
• first and second dielectric portions positioned on opposite side portions of the semiconductor portion and on opposite side portions of the source region;
• and
• first and second gate structures projecting from said substrate and insulated from the doped source region and the body region by the dielectric portions.

A method for manufacturing a vertical power MOS transistor, comprising:

• forming a superficial first semiconductor layer of a first type of conductivity on a semiconductor substrate of the first type of conductivity;
• forming trench regions having tapered walls in said first semiconductor layer;
• forming semiconductor portions of a second type of conductivity contained in said first semiconductor layer by filling in said trench regions with a second semiconductor layer of a second type of conductivity with a charge concentration which compensates or balances a charge concentration of the first type of conductivity of said first semiconductor;
• forming respective implanted body regions of said second type of conductivity by carrying out a first ion implantation of a first type of dopant in said semiconductor portions;
• forming an implanted source region of said first type of conductivity inside one of said implanted body regions by carrying out a second ion implantation of a second type of dopant in said one of said implanted body regions;
• carrying out an activation thermal process of said first and second type of dopant said implanted body and source regions at between 1400° and 1600° C.;
• and
• forming gate structures of said vertical power MOS transistor on said semiconductor substrate, after forming said implanted body and source regions.