Thin Film Transistor Array Panel and Method for Manufacturing the Same

A method of manufacturing a thin film transistor array panel, comprising:

• forming a gate electrode including a metal that can be combined with silicon to form silicide;
• forming a first silicon nitride layer on the gate electrode by supplying a gas which includes silicon and a gas which includes nitrogen;
• forming a second silicon nitride layer by supplying a gas which includes silicon and a gas which includes nitrogen on the first silicon nitride layer, wherein a flow amount ratio of the two gases is different from a flow amount ratio supplied for forming the first silicon nitride layer;
• forming a semiconductor on the second silicon nitride layer;
• forming a data line and a drain electrode on the semiconductor;
• and
• forming a pixel electrode connected to the drain electrode,
• wherein a [N—H]/[Si—H] binding number ratio of the second silicon nitride layer is less than that of the first silicon nitride layer.

A thin film transistor array panel comprising:

• a gate electrode including a metal that can be combined with silicon to form silicide;
• a semiconductor formed under or over the gate electrode;
• a gate insulation layer formed between the gate electrode and the semiconductor;
• a source electrode and a drain electrode that contact the semiconductor;
• and
• a pixel electrode connected to the drain electrode,
• wherein the gate insulation layer includes a first silicon nitride layer and a second silicon nitride layer interposed between the first silicon nitride layer and the semiconductor, and
• wherein a [N—H]/[Si—H] binding number ratio of the first silicon nitride layer is greater than that of the second silicon nitride layer.

A thin film transistor array panel comprising:

• a gate electrode including a metal that can be combined with silicon to form silicide;
• a semiconductor formed under or over the gate electrode;
• a gate insulation layer interposed between the gate electrode and the semiconductor, wherein the gate insulation layer comprises silicon nitride;
• a source electrode and a drain electrode that contact the semiconductor;
• and
• a pixel electrode connected to the drain electrode,
• wherein the gate insulation layer comprises a contact unit that contacts the gate electrode, a channel unit that contacts the semiconductor, and a middle unit interposed between the contact unit and the channel unit, and
• wherein the contact unit and the middle unit have different [N—H]/[Si—H] binding number ratios.