Method for determining electro-migration failure mode

A method for analyzing integrated circuits, the method comprising:

• forming a plurality of first test structures identical to each other, wherein each of the first test structures comprises a first via structure connected to a first metal line;
• stress testing the plurality of first test structures to obtain a first plurality of failure times;
• plotting the first plurality of failure times on a plot illustrating accumulative failure rates as a function of failure time;
• forming a plurality of second test structures identical to each other, wherein each of the second test structures comprises a second via structure connected to a second metal line, and wherein the second via structure has a substantially different cross-sectional area from the first via structure, and wherein the first metal line and the second metal line are substantially identical;
• stress testing the plurality of second test structures to obtain a second plurality of failure times;
• plotting the second plurality of failure times on the plot;
• determining substantially overlapping portions of the first and the second plurality of failure times to determine a dividing point between intrinsic failures and early failures;
• and
• determining early failures of the plurality of first test structures, wherein the early failures have shorter failure times than the dividing point.