Field effect transistor and fabrication thereof, semiconductor device and fabrication thereof, logic circuit including the semiconductor device, and semiconductor substrate

A method of fabricating a field effect transistor, comprising the steps of:

• forming a semiconductor substrate in such a manner that a semiconductor layer having a strain effect is formed in an upper layer of said semiconductor substrate;
• forming a gate electrode on said semiconductor layer having the strain effect through a gate insulating film;
• and
• forming a source/a drain by doping an impurity for forming the source/drain in said semiconductor layer having the strain effect on both sides of said gate electrode.

A method of fabricating a semiconductor device, comprising the steps of:

• forming a semiconductor substrate in such a manner that a silicon layer having a strain effect is formed in an upper layer of said semiconductor substrate, a relax layer is formed below the silicon layer having the strain effect, and a buffer layer below the relax layer;
• forming a gate electrode of a p-channel type field effect transistor and a gate electrode of a-n channel type field effect transistor on said strain effect silicon layer through a gate insulating film;
• forming a source and a drain each composed of p-type diffusion layer in only said strain effect silicon layer on both sides of said gate electrode of said p-channel type field effect transistor, the source and drain of the p-type diffusion layers being formed to a depth of less than a depth of the strain effect silicon layer;
• forming a source and a drain each composed of n-type diffusion layers in only said strain effect silicon layer on both sides of said gate electrode of said n-channel type field effect transistor, the source and drain of the n-type diffusion layers being formed to a depth of less than a depth of the strain effect silicon layer;
• forming a isolation region in between the p-channel type field effect transistor and the n-channel type field effect transistor in said silicon layer having the strain effect;
• and
• wherein the buffer layer is constructed of a P− type silicon germanium, wherein the relax layer is made from a P− type silicon germanium whose stress is relaxed.

A method of fabricating a semiconductor device, comprising the steps of:

• forming a semiconductor substrate by forming a buffer layer on a silicon base layer, wherein the buffer layer is made of a P− type silicon germanium,
• forming a relax layer on the buffer layer, wherein the relax layer is formed of P− type silicon germanium which is relaxed, and
• forming a silicon strain effect layer on the relax layer;
• forming a gate electrode of a p-channel type field effect transistor and a gate electrode of a n-channel type field effect transistor on said strain effect silicon layer through a gate insulating film;
• forming a source and a drain each composed of p-type diffusion layers only in said silicon layer having the strain effect on both sides of said gate electrode of said p-channel type field effect transistor, the source and drain of the p-type diffusion layers being formed to a depth of less than a depth of the strain effect silicon layer;
• forming a source and a drain each composed of n-type diffusion layers only in said strain effect silicon layer on both sides of said gate electrode of said n-channel type field effect transistor, the source and drain of the n-type diffusion layers being formed to a depth of less than a depth of the strain effect silicon layer;
• and
• forming a isolation region in between the p-channel type field effect transistor and the n-channel type field effect transistor in said strain effect silicon layer.