US 2008/0175084 A1Published application

Semiconductor memory device and sense amplifier circuit

AssigneesHitachi, Ltd., Elpida Memory, Inc.

InventorsSatoru AKIYAMA, Tomonori Sekiguchi, Riichiro Takemura, Hiroaki Nakaya, Shinichi Miyatake, Yuko Watanabe

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Abstract

A semiconductor memory device having high integration, low consumption power and high operation speed compatible to each other including a sense amplifier circuit having plural pull-down circuits and a pull-up circuit, in which a transistor constituting one of plural pull-down circuits has a larger constant than that of a transistor constituting other pull-down circuits, for example, a channel length and a channel width, a pull-down circuit having a larger constant of the transistor in the plural pull-down circuits is precedingly activated and then another pull-down circuit and the pull-up circuit are activated to conduct reading and, further, the data line and the precedingly driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

Claims25

Dependent claims

A semiconductor device comprising:

a memory array having a plurality of word lines, a plurality of data lines, and a plurality of memory cells arranged each at the intersection of each of the plurality of word lines and the plurality of data lines, and
a sense amplifier circuit connected to each of the plurality of data line pairs including the plurality of the data lines,
wherein the sense amplifier circuit has a first MISFET pair, a second MISFET pair, and a third MISFET pair,
the first and second MISFET pair are a first conduction type and the third MISFET pair are a second conduction type which is opposite to the first conduction type,
a gate of one of the first MISFET pair and a data line, which is included in the plurality of data lines and is provided corresponding to a drain of the other of the first MISFET pair, are connected with each other,
a gate of one of the second MISFET and a drain of the other of second MISFET are connected with each other,
a gate of one of the third MISFET pair and a drain of the other of the third MISFET are connected with each other,
the first MISFET pair has a transistor pair including a first transistor having the first conduction type and a second transistor having the first conduction type,
the drain of the first transistor is connected with the source of a fourth MISFET having the first conduction type,
the drain of the second transistor is connected with the source of a fifth MISFET having the first conduction type, and
drains of the fourth and fifth MISFETs are connected to the data line pair, respectively.

8 more elements

A semiconductor device comprising:

a memory array having a plurality of word lines, a plurality of data lines, and a plurality of memory cells arranged each at the intersection of each of the plurality of word lines and the plurality of data lines, and
a sense amplifier circuit connected to each of the plurality of data line pairs including the plurality of the data lines,
wherein the sense amplifier circuit has a first MISFET pair, a second MISFET pair, and a third MISFET pair,
the first and second MISFET pair are a first conduction type and the third MISFET pair are a second conduction type which is opposite to the first conduction type,
a gate of one of the first MISFET pair and a data line, which is included in the plurality of data lines and is provided corresponding to a drain of the other of the first MISFET pair, are connected with each other,
a gate of one of the second MISFET and a drain of the other of second MISFET are connected with each other,
a gate of one of the third MISFET pair and a drain of the other of the third MISFET are connected with each other, and
a first circuit for driving the first source line of the first MISFET pair from a third voltage to a first voltage,
the threshold voltage for each of MISFETs of the first MISFET pair is lower than that for each of the MISFET of the second MISFET pair, and
the gate voltage for the first circuit is changed from the first voltage that keeps the first circuit in an off-state to a second voltage that turns the circuit to an on-state, to change the voltage for the first source line of the first MISFET pair from the third voltage to the first voltage, thereby driving the first MISFET pair preceding to the second MISFET pair and the third MISFET pair.

7 more elements

Dependencies are inferred from the claim text.